Synopsys RedHawk-SC

Built on the SeaScape™ platform, RedHawk-SC supports near-linear scalability across tens of thousands of CPU cores, enabling ultra-large, full-chip analysis with low memory requirements for all cores and seamless integration into cloud environments. 

Supports multi-scenario activity patterns, including simulation vector-based, vectorless and SigmaDVD, to capture dynamic power supply noise. Supports in-rush current analysis for power-gated designs to evaluate ramp-up impact. 

Breakthrough SigmaDVD technology delivers comprehensive local coverage of dynamic voltage drop with root-cause identification of top victims and aggressors, uncovering missed scenarios in a fraction of the runtime of conventional transient methods. Building on SigmaDVD, SigmaAV extends coverage to regional and off-chip package effects, ensuring reliable power distribution across activity scenarios. Together, they transform voltage analysis into application-aware workflows through advanced voltage insights. 

Reduced-Order Models (ROM) accelerate chip-level analysis, enabling rapid iteration and early identification of top-level power grid issues while significantly reducing compute requirements. ROM maintains high accuracy for top-level analysis and provides an efficient way to identify grid construction issues and quantify packaging impact.

Comprehensive electromigration (EM) analysis evaluates current density reliability across power and signal interconnects with statistical EM budgeting. The EM analysis includes thermal effects due to self-heating of transistors and interconnect (Joule heating), which avoids reliability risks and ensures long-term device performance.

Built on RedHawk-SC’s unique comprehensive coverage, root cause analytics, and what-if analysis capabilities, natively integrated solutions with Synopsys Fusion Compiler, PrimeClosure, and PrimeTime incorporate voltage drop as an optimization metric during physical design, deliver an automated timing-driven voltage drop ECO flow that achieves high fix rates with minimal design impact, and reduce margin pessimism and minimize timing escapes through voltage-aware timing signoff.

Chip Power Models (CPMs), Chip Thermal Models (CTMs), Custom Macro Models (CMM) enable a seamless chip-to-system workflow with Synopsys Totem-SC and RedHawk-SC Electrothermal. These models enable efficient hierarchical power and electrothermal co-simulation of analog IP, chip, package and system power delivery network (PDN) for both single and multi-die designs. 

High-fidelity power integrity analysis uses an advanced extractor optimized for non-Manhattan geometries, and a Full-Resolution IR Model (FIRM) with per-bump granularity enables hierarchical analysis of complex multi-die designs. Seamless integration with 3DIC Compiler enables correct-by-construction design, avoiding costly late-stage surprises. 

Supports next-generation AI-driven agentic design workflows that require fast evaluation of multiple design scenarios without repeated full-chip processing, accelerating AI-assisted power integrity analysis, decision-making, and design exploration beyond traditional signoff.